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Hermetically Sealed, Transistor Output Optocouplers for Analog and Digital Applications
Technical Data
Agilent 4N55*, 5962-87679, HCPL-553X, HCPL-653X, HCPL-257K, HCPL-655X, 5962-90854, HCPL-550X
*See matrix for available extensions. Features * Dual Marked with Device Part Number and DSCC Drawing Number * Manufactured and Tested on a MIL-PRF-38534 Certified Line * QML-38534, Class H and K * Five Hermetically Sealed Package Configurations * Performance Guaranteed, Over -55C to +125C * High Speed: Typically 400 kBit/s * 9 MHz Bandwidth * Open Collector Output * 2-18 Volt VCC Range * 1500 Vdc Withstand Test Voltage * High Radiation Immunity * 6N135, 6N136, HCPL-2530/2531, Function Compatibility * Reliability Data
Description These units are single, dual and quad channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full MIL-PRF-38534 Class Level H or K testing or from the appropriate DSCC Drawing. All devices are manufactured and tested on a MIL-PRF38534 certified line and are included in the DSCC Qualified Manufacturers List QML-38534 for Hybrid Microcircuits.
Applications * Military and Space * High Reliability Systems * Vehicle Command, Control, Life Critical Systems * Line Receivers * Switching Power Supply * Voltage Level Shifting * Analog Signal Ground Isolation (see Figures 7, 8, and 13) * Isolated Input Line Receiver * Isolated Output Line Driver * Logic Ground Isolation * Harsh Industrial Environments * Isolation for Test Equipment Systems
The connection of a 0.1 F bypass capacitor between VCC and GND is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Each channel contains a GaAsP light emitting diode which is optically coupled to an integrated photon detector. Separate connections for the photodiodes and output transistor collectors improve the speed up to a hundred times that of a conventional phototransistor optocoupler by reducing the base-collector capacitance. These devices are suitable for wide bandwidth analog applications, as well as for interfacing TTL to LSTTL or CMOS. Current Transfer Ratio (CTR) is 9% minimum at IF = 16 mA. The 18 V VCC capability will enable the designer to interface any TTL family to CMOS. The availability of the base lead allows optimized gain/ bandwidth adjustment in analog applications. The shallow depth of the IC photodiode provides better radiation immunity than conventional phototransistor couplers.
These products are also available with the transistor base node not connected to improve common mode noise immunity and ESD susceptibility. In addition, higher CTR minimums are available by special request. Package styles for these parts are 8 and 16 pin DIP through hole (case outlines P and E respectively), 16 pin DIP flat pack (case outline F), and leadless ceramic chip carrier (case outline 2). Devices may be purchased with a variety of lead bend and plating options, see Selection Guide Table for details. Standard Microcircuit Drawing (SMD) parts are available for each package and lead style. Because the same functional die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifications, and performance
characteristics shown in the figures are identical for all parts. Occasional exceptions exist due to package variations and limitations and are as noted. Additionally, the same package assembly processes and materials are used in all devices. These similarities give justification for the use of data obtained from one part to represent other part's performance for die related reliability and certain limited radiation test results. Truth Table (Positive Logic)
Input On (H) Off (L) Output L H
Functional Diagram Multiple Channel Devices Available
V CC VB VO
GND
2
Selection Guide-Package Styles and Lead Configuration Options
16 Pin DIP Package Lead Style Channels Common Channel Wiring Agilent Part No. and Options Commercial MIL-PRF-38534 Class H MIL-PRF-38534 Class K Standard Lead Finish Solder Dipped* Butt Joint/Gold Plate Gull Wing/Soldered* Class H SMD Part # Prescript for all below Either Gold or Soldered Gold Plate Solder Dipped* Butt Joint/Gold Plate Butt Joint/Soldered* Gull Wing/Soldered* Class K SMD Part # Prescript for all below Either Gold or Soldered Gold Plate Solder Dipped* Butt Joint/Gold Plate Butt Joint/Soldered* Gull Wing/Soldered*
1. JEDEC registered part. * Solder contains lead
8 Pin DIP Through Hole 1 None HCPL-5500 HCPL-5501 HCPL-550K Gold Plate Option 200 Option 100 Option 300 59629085401HPX 9085401HPC 9085401HPA 9085401HYC 9085401HYA 9085401HXA 59629085401KPX 9085401KPC 9085401KPA 9085401KYC 9085401KYA 9085401KXA
8 Pin DIP Through Hole 2 VCC GND HCPL-5530 HCPL-5531 HCPL-553K Gold Plate Option 200 Option 100 Option 300 59628767902PX 8767902PC 8767902PA 8767902YC 8767902YA 8767902XA 59628767906KPX 8767906KPC 8767906KPA 8767906KYC 8767906KYA 8767906KXA
16 Pin Flat Pack 4 VCC GND HCPL-6550 HCPL-6551 HCPL-655K Gold Plate
20 Pad LCCC
Through Hole 2 None 4N55(1) 4N55/883B HCPL-257K Gold Plate Option 200 Option 100 Option 300 59628767901EX 8767901EC 8767901EA 8767901UC 8767901UA 8767901TA 59628767905KEX 8767905KEC 8767905KEA 8767905KUC 8767905KUA 8767905KTA
Unformed Leads Surface Mount 2 None HCPL-6530 HCPL-6531 HCPL-653K Solder Pads
59628767904FX 8767904FC
596287679032X 87679032A
59628767908KFX 8767908KFC
59628767907K2X 8767907K2A
3
8 Pin Ceramic DIP Single Channel Schematic
2 + VF CATHODE 3 5 IF ICC IB IO 8 7 6 V CC VB VO
ANODE
GND
Note, base is pin 7.
Functional Diagrams
16 Pin DIP Through Hole 2 Channels
1 V B1 V CC1 V O1 GND 16
8 Pin DIP Through Hole 1 Channel
8 Pin DIP Through Hole 2 Channels
16 Pin Flat Pack Unformed Leads 4 Channels
1 16
20 Pad LCCC Surface Mount 2 Channels
15 14 V CC2 19 20 V B2 V O2 GND 2 V O1 GND 1 V CC1 V B1 7 8 13 12
1
2 3 15
V CC VB V OUT
8
1
V CC V O1 V O2
8
2 V CC V O1 V O2 V O3 V O4 GND 15 14
2
14
7 6
2 3
7
3
3
4 13
6
4 13
2 3
10 9
4
5 V B2 V CC2 GND V O2 12
GND
5
4
GND
5
5 12
6 7
11 10
6 7
11 10
8
9
8
9
Note: 8 pin DIP and flat pack devices have common VCC and ground. 16 pin DIP and LCCC (leadless ceramic chip carrier) packages have isolated channels with separate VCC and ground connections.
Outline Drawings 16 Pin DIP Through Hole, 2 Channels
20.06 (0.790) 20.83 (0.820) 0.89 (0.035) 1.65 (0.065) 4.45 (0.175) MAX. 8.13 (0.320) MAX.
0.51 (0.020) MIN.
3.81 (0.150) MIN.
0.20 (0.008) 0.33 (0.013)
2.29 (0.090) 2.79 (0.110)
0.51 (0.020) MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
4
Leaded Device Marking
Agilent DESIGNATOR Agilent P/N DSCC SMD* DSCC SMD* PIN ONE/ ESD IDENT A QYYWWZ XXXXXX XXXXXXX XXX XXX 50434 * QUALIFIED PARTS ONLY COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Agilent CAGE CODE*
Leadless Device Marking
Agilent DESIGNATOR Agilent P/N PIN ONE/ ESD IDENT COUNTRY OF MFR. A QYYWWZ XXXXXX XXXX XXXXXX XXX 50434 * QUALIFIED PARTS ONLY COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) DSCC SMD* DSCC SMD* Agilent CAGE CODE*
Outline Drawings 16 Pin Flat Pack, 4 Channels
7.24 (0.285) 6.99 (0.275) 2.29 (0.090) MAX.
1.27 (0.050) REF. 11.13 (0.438) 10.72 (0.422)
0.46 (0.018) 0.36 (0.014) 8.13 (0.320) MAX.
2.85 (0.112) MAX.
0.88 (0.0345) MIN. 0.89 (0.035) 0.69 (0.027) 5.23 (0.206) MAX. 9.02 (0.355) 8.76 (0.345)
0.31 (0.012) 0.23 (0.009)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
20 Terminal LCCC Surface Mount, 2 Channels
8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 1.02 (0.040) (3 PLCS) 1.14 (0.045) 1.40 (0.055) 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205)
8 Pin DIP Through Hole, 1 and 2 Channel
9.40 (0.370) 9.91 (0.390) 0.76 (0.030) 1.27 (0.050) 4.32 (0.170) MAX. 8.13 (0.320) MAX. 7.16 (0.282) 7.57 (0.298)
TERMINAL 1 IDENTIFIER 2.16 (0.085) METALIZED CASTILLATIONS (20 PLCS) 0.64 (0.025) (20 PLCS) 0.51 (0.020)
0.51 (0.020) MIN.
3.81 (0.150) MIN.
1.78 (0.070) 2.03 (0.080)
0.20 (0.008) 0.33 (0.013)
1.52 (0.060) 2.03 (0.080)
2.29 (0.090) 2.79 (0.110)
0.51 (0.020) MAX.
7.36 (0.290) 7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: DIMENSIONS IN MILLIMETERS (INCHES). SOLDER THICKNESS 0.127 (0.005) MAX.
5
Hermetic Optocoupler Options
Option 100 Description Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details).
4.32 (0.170) MAX.
0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110)
1.14 (0.045) 1.40 (0.055) 0.51 (0.020) MAX.
4.32 (0.170) MAX.
0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110)
1.14 (0.045) 1.40 (0.055) 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310)
200
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 and 16 pin DIP. DSCC drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a standard feature. Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). This option has solder dipped leads.
4.57 (0.180) MAX.
300
0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110)
1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX.
4.57 (0.180) MAX. 0.20 (0.008) 0.33 (0.013) 9.65 (0.380) 9.91 (0.390)
4.57 (0.180) MAX.
0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110)
1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX.
5 MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
6
Absolute Maximum Ratings No derating required up to +125 C.
Parameter Storage Temperature Range Operating Ambient Temperature Junction Temperature Case Temperature Lead Solder Temperature (1.6 mm below seating plane) Average Input Forward Current Peak Forward Input Current (each channel, 1 ms duration) Reverse Input Voltage Average Output Current, each channel Peak Output Current, each channel Supply Voltage Output Voltage Input Power Dissipation, each channel Output Power Dissipation, each channel Package Power Dissipation, each channel PD IF AVG IFPK BVR IO IO VCC VO -0.5 -0.5 Symbol TS TA TJ TC Min. -65 -55 Max. +150 +125 +175 +170 260 for 10 s 20 40 Units C C C C C mA mA
See Electrical Characteristics 8 16 20 20 36 50 200 mA mA V V mW mW mW
Single Channel 8 Pin, Dual Channel 16 Pin, and LCCC Only
Emitter Base Reverse Voltage Base Current, each channel VEBO IB 3 5 V mA
ESD Classification (MIL-STD-883, Method 3015)
4N55, 4N55/883B, HCPL-257K, HCPL-5500/01/0K, and HCPL-6530/31/3K HCPL-5530/31/3K, HCPL-6550/51/5K (), Class 1 (Dot), Class 3
Recommended Operating Conditions
Parameter Input Current, Low Level Input Current, High Level Supply Voltage, Output Symbol IFL IFH VCC 12 2 Min. Max. 250 20 18 Units A mA V
7
Electrical Characteristics TA = -55 C to +125 C, unless otherwise specified. See Note 12.
Parameter Symbol Group A, Subgroup 1, 2, 3 1, 2, 3 Test Conditions Limits Min. Typ.* Max. VO = 0.4V, IF = 16 mA, VCC = 4.5V IF = 0, IF (other channels) = 20 mA VO = VCC = 18 V IF = 250 A, IF (other channels) = 20 mA, VO = VCC = 18 V VI-O = 1500 Vdc, RH 65%, TA = 25C, t = 5 s IF = 20 mA 1.55 9 20 5 100 % A 2, 3 4 1, 2, 10 1 Units Fig. Notes
Current Transfer Ratio Logic High Output Current
CTR IOH
Output Leakage Current
IOLeak
1, 2, 3
30
250
A
4
1
Input-Output Insulation Leakage Current Input Forward Voltage
II-O
1
1.0
A
3, 9
VF
1, 2, 3
1.8 1.9
V
1
1, 14 1, 13
Reverse Breakdown Voltage
BVR
1, 2, 3
IR = 10 A
5 3
V
1, 14 1, 13
Logic High Supply Current
Single Channel Dual Channel Quad Channel
ICCH
1, 2, 3
VCC = 18 V, IF = 0 mA VCC = 18 V, IF = 0 mA (all channels) VCC = 18 V, IF = 0 mA (all channels)
0.1 0.2 0.4 35 70 140 1.0 0.4
10 20 40 200 400 800 6.0 2.0
A
1 1,4 1
Logic Low Supply Current
Single Channel Dual Channel Quad Channel
ICCL
1, 2, 3
VCC = 18 V, IF = 20 mA VCC = 18 V, IF1 = IF2 = 20 mA VCC = 18 V, IF1 = IF2 = IF3 = IF4 = 20 mA
A
1 1, 4 1
Propagation Delay Time to Logic High at Output Propagation Delay Time to Logic Low at Output
tPLH tPHL
9, 10, 11
RL = 8.2 k, CL = 50 pF, IF = 16 mA, VCC = 5 V
s
6, 9
1, 6
*All typical values are at VCC = 5 V, TA = 25C.
8
Typical Characteristics All typical values are at TA = 25C, VCC = 5 V, unless otherwise specified.
Parameter Input Capacitance Input Diode Temperature Coefficient Resistance (Input-Output) Capacitance (Input-Output) Transistor DC Current Gain Small Signal Current Transfer Ratio Common Mode Transient Immunity at Logic High Level Output Common Mode Transient Immunity at Logic Low Level Output Bandwidth Symbol CIN VF/TA RI-O C I-O hFE IO/IF |CM H| Test Conditions VF = 0 V, f = 1 MHz IF = 20 mA VI-O = 500 V f = 1 MHz VO = 5 V, IO = 3 mA VCC = 5 V, VO = 2 V IF = 0 mA, RL = 8.2 k, VO (min) = 2.0 V, VCM = 10 VP-P IF = 16 mA, RL = 8.2 k, VO (max) = 0.8 V, VCM = 10 VP-P Typ. 60 -1.5 1012 1.0 250 21 1000 Units pF mV/C pF % V/s 7 10 Fig. Notes 1 1 3 1, 11 1 1 1, 7
|CM L|
-1000
V/s
10
1, 7
BW
9
MHz
8
8
Multi-Channel Product Only
Parameter Input-Input Insulation Leakage Current Resistance (Input-Input) Capacitance (Input-Input)
Symbol II-I RI-I CI-I
Test Conditions RH 65%, VI-I = 500 V, t = 5 s VI-I = 500 V f=1 MHz
Typ. 1 1012 0.8
Units pA pF
Notes 5, 9 5 5
Notes: 1. Each channel of a multi-channel device. 2. Current Transfer Ratio is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100%. CTR is known to degrade slightly over the unit's lifetime as a function of input current, temperature, signal duty cycle, and system on time. Refer to Application Note 1002 for more detail. ln short, it is recommended that designers allow at least 20-25% guardband for CTR degradation. 3. All devices are considered two-terminal devices; measured between all input leads or terminals shorted together and all output leads or terminals shorted together. 4. The 4N55, 4N55/883B, HCPL-257K, HCPL6530, HCPL-6531, and HCPL-653K dual channel parts function as two independent single channel units. Use the single channel parameter limits. IF = 0 mA for channel under test and I F = 20 mA for other channels. 5. Measured between adjacent input pairs shorted together for each multichannel device.
6. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point on the trailing edge of the output pulse. 7. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO > 2.0 V). 8. Bandwidth is the frequency at which the ac output voltage is 3 dB below the low frequency asymptote. For the HCPL-5530 the typical bandwidth is 2 MHz. 9. This is a momentary withstand test, not an operating condition.
10. Higher CTR minimums are available to support special applications. 11. Measured between each input pair shorted together and all output connections for that channel shorted together. 12. Standard parts receive 100% testing at 25C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and -55C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 13. Not required for 4N55, 4N55/883B, HCPL257K, 5962-8767901, and 5962-8767905 types. 14. Required for 4N55, 4N55/883B, HCPL-257K, 5962-8767901, and 5962-8767905 types only.
9
Figure 1. Input Diode Forward Current vs. Forward Voltage.
Figure 2. DC and Pulsed Transfer Characteristic.
Figure 3. Normalized Current Transfer Ratio vs. Input Diode Forward Current.
IOH - LOGIC HIGH OUTPUT CURRENT - A
100
IF = 250 A, IF (OTHER CHANNELS) = 20 mA IF = 0 A, IF (OTHER CHANNELS) = 20 mA IF = IF (OTHER CHANNELS) = 0 mA
10
1
0.1
VCC = VO = 18 V
0.01 0.001 -60 -40 -20 0
20 40 60 80 100 120 140
TA - TEMPERATURE - C
Figure 4. Logic High Output Current vs. Temperature.
Figure 5. Logic Low Supply Current vs. Input Diode Forward Current.
Figure 6. Propagation Delay vs. Temperature.
Figure 7. Normalized Small Signal Current Transfer Ratio vs. Quiescent Input Current.
10
+12 V 0.1 F V IN 51 1k 0.1 F 2.1 k 47 F Q1 100 RF
D.U.T. V CC VO VB 15 k
+12 V 1.2 k 9.1 k Q2 100 470 Q3 0.01 F 0.01 F VO (1 M, 12 pF TEST INPUT)
GND 22 1N4150
SINGLE CHANNEL TESTING, INDEPENDENT VCC DEVICES
TRIM FOR UNITY GAIN Q 1 , Q 2 , Q 3 : 2N3904 TYPICAL LINEARITY = +3 % AT V IN = 1 V P-P TYPICAL SNR = 50 dB TYPICAL R F = 375 TYPICAL V O dc = 3.8 V TYPICAL IF = 9 mA
+5 V SET I F AC INPUT 0.1 F 560 100 20 k 2N3053 1.6 Vdc 0.25 V P-P ac
D.U.T. V CC 100
+15 V
NORMALIZED RESPONSE - dB
+15 +10 +5 0 -5 -10 -15 -20 0.1 1.0 10 f - FREQUENCY - MHz 100 COMMON V CC DEVICES T A = 25 C INDEPENDENT V CC DEVICES
VO
GND
COMMON V CC DEVICES
Figure 8. Frequency Response.
PULSE GEN. Z O = 50 t r = 5 ns
IF
D.U.T. V CC RL
+5 V
IF MONITOR 100 GND
VO C L * = 50 pF
SINGLE CHANNEL OR COMMON V CC DEVICES
10 % DUTY CYCLE 1/f < 100 s NOTES: * C L INCLUDES PROBE AND STRAY WIRING CAPACITANCE. BASE LEAD NOT CONNECTED.
Figure 9. Switching Test Circuit.* *JEDEC Registered Data.
11
IF B RM D.U.T. V CC A RL VO
+5 V
V FF
GND SINGLE CHANNEL OR COMMON V CC DEVICES V CM + PULSE GEN.
NOTE: BASE LEAD NOT CONNECTED.
Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.
5V V CC
220 D.U.T. V CC TTL LOGIC GATE 0.01 F GND EACH CHANNEL RL
Logic Family Device No. VCC RL 5% Tolerance
LSTTL 54LS14 5V 18 k *
CMOS CD40106BM 5V 8.2 k 15 V 22 k
*The equivalent output load resistance is affected by the LSTTL input current and is approximately 8.2 k. This is a worst case design which takes into account 25% degradation of CTR. See App. Note 1002 to assess actual degradation and lifetime.
Figure 11. Recommended Logic Interface.
V CC D.U.T.* VCC (EACH INPUT) + V IN 0.1 F VO GND NOMINAL CONDITIONS PER CHANNEL: IF = 20 mA IO = 4 mA ICC = 30 A NOTE: BASE LEAD NOT CONNECTED. T A = +125 C (EACH OUTPUT) VOC
Figure 12. Operating Circuit for Burn-In and Steady State Life Tests. All Channels Tested Simultaneously.
12
HCPL-5530 U1 + IF 1 1 8 IC 2 V IN IF 2 7
2 220 U3 + 2
R3
OFFSET ADJUST 5k
+
1
3 U2 + R1 2.7 k U 1 , U 2 , U 3 , U 4 , LM307 IC =K1 IF IF IF IF n1
1
6
IC
2
R 4 1 k 5 k GAIN ADJUST R5 50 k V OUT
-
4
5 -15 V U4 + 2
R2 2.7 k
1
6 mA
I CC
2
1
n2 -15 V
2
IC
2
=K2
Figure 13. Isolation Amplifier Application Circuit.
Description The schematic uses a dualchannel, high-speed optocoupler (HCPL-5530) to function as a servo type dc isolation amplifier. This circuit operates on the principle that two optocouplers will track each other if their gain changes by the same amount over a specific operating region.
Performance of Circuit * 1% linearity for 10 V peakto-peak dynamic range * Gain drift: -0.03%/C * Offset Drift: 1 mV/C * 25 kHz bandwidth (limited by Op-Amps U1, U2)
MIL-PRF-38534 Class H, Class K, and DSCC SMD Test Program Agilent's Hi-Rel Optocouplers are in compliance with MILPRF-38534 Classes H and K. Class H and Class K devices are also in compliance with DSCC drawings 5962-87679, and 5962-90854. Testing consists of 100% screening and quality conformance inspection to MIL-PRF-38534.
13
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For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright (c) 2004 Agilent Technologies, Inc. December 10, 2004 5989-1659EN

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